SV.3 SystemVerilog for Digital Design (RTL)

Welcome!

• Goal: Learn to write synthesizable SystemVerilog code (RTL) for designing digital hardware components, focusing on good practices for synthesis and industry relevance.
• Target Audience: Senior students and recent graduates in Electrical Engineering with focus on Digital Systems, and practicing Digital Design Engineers (RTL Designers).
• Prerequisites: Course 1 (SystemVerilog Fundamentals), Solid Digital Logic background, Computer Architecture basics.

Course Outline

1. RTL Design Principles and Styles
2. Synthesizable Constructs – Combinational Logic
3. Synthesizable Constructs – Sequential Logic
4. Finite State Machine (FSM) Design
5. Hierarchy, Parameters, and Generate Blocks
6. Introduction to Synthesis and Design Compiler (DC)
7. Introduction to Design for Test (DFT)
8. Introduction to Power-Aware Design (RTL)

Prerequisites Review

• Assumed Knowledge from Course 1: SystemVerilog syntax, data types (logic, bit, int), modules, ports, parameters, operators, assign, basic procedural blocks (initial, always), if/case.
• Assumed Knowledge (Conceptual):
  • Digital Logic Design: Combinational circuits (gates, MUX, ALU), Sequential circuits (latches, flip-flops), Finite State Machines (FSMs), Datapaths, Control Units.
  • Computer Architecture Basics: CPU components, memory interfaces, buses.

Learning Objectives

• By the end of this course, you will be able to:
  • Define RTL (Register Transfer Level) design and apply synchronous design principles.
  • Write synthesizable SystemVerilog code for combinational logic using assign, always_comb, and functions.
  • Write synthesizable SystemVerilog code for sequential logic using always_ff and correctly apply blocking vs. non-blocking assignments.
  • Implement Finite State Machines (FSMs) using standard coding styles.
  • Utilize hierarchy, parameters, generate blocks, and interfaces for modular and reusable design.
  • Understand the basic process of logic synthesis and interpret simple reports from Synopsys Design Compiler (DC).
  • Describe fundamental Design for Test (DFT) concepts like scan chains.
  • Implement basic power-aware design techniques like clock gating at the RTL level.