Connecting the Dots: From Physics to Packaged SOCs

Overview

This course aims to ground the students in the fundamentals and the overall flow before they dive into the specialized courses. Providing the “big picture” context will significantly enhance their understanding and appreciation of the subsequent detailed material.

Here is a comprehensive outline and content for the 1-day (approx. 8-hour) introductory mini-course.

Details

This course serves as a prequel to the main IC development training program.

To help students better grasp the “big picture” view of IC design field, before embarking on our comprehensive training program, we want to review and connect the dots of all important fundamental concepts top down and end-to-end, covering from the end result of a hardware system as implemented in a silicon IC system-on-chip (SOC) to the physics of electricity in matter.

Thus, the end-to-end connection includes but not be limited to the following:

1. An electrical system implemented as a hardware embedded computer system in a silicon IC system-on-chip (SOC), driven by power supply source and timed by quartz crystal that supplies the timing signal for synchronizing the operation
2. design flow that takes the RTL models in SystemVerilog HDL to the fabricated SOC
3. computer system architecture
4. logic design
5. Reasonings behind the modeling constructs such as the 4 state logic
6. Reasonings for clocking
7. logic cell primitives (inverter, NAND, NOR) as fundamental building blocks of logic design
8. CMOS transistor as building blocks of logic cell primitives
9. Ideal basic circuit elements in electric circuits as mathematical model for electrical systems
10. the physics of electric currents that makes propagation of electric signals possible
11. Definition of signal and electric signal
12. Power supply source for an SOC design
13. Timing source for an SOC design

To further make the connections, a number of questions that we also want to address and provide answers to students regarding the principal inputs into a system, specifically, power, clocking, and reset:

1. What power supplies are typically applied to drive a system with SOCs implemented in submicron technology nodes?
2. What voltage levels are typically used, and why?
3. What level of power consumptions or power dissipation are typical?
4. How is it possible to model and verify a design in RTL modeling with zero delays except for the clocking?
5. How is it possible to model and verify signal delays in a design separately from RTL modeling?
6. How is it possible to model and verify voltage, current and power in a design separately from RTL modeling?
7. How is it possible to model and verify effects of electric and magnetic field coupling  in a design separately from RTL modeling?
8. What is the importance of power-on reset, and how is it generated and applied?

Finally, we want to touch on the most frequently encountered difficulties that students and engineers face in designing and verifying SOC designs.

Target Audience

4th-year students and recent graduates in Electrical Engineering with background in logic design, computer architecture, SOC architecture.