SV.2: SystemVerilog for Cell Library Modeling

Welcome!

• Goal: Understand and use SystemVerilog features to model the functionality, timing, and basic power aspects of standard cells and macro cells for simulation.
• Target Audience: Library development/characterization engineers, designers/verification engineers needing to understand low-level models.
• Prerequisites: Course 1 (SystemVerilog Fundamentals).
• Duration: 1 Week (Full-Time Equivalent)

Course Outline

1. Purpose and Structure of Library Models
2. Modeling Combinational Logic Functionality
3. Modeling Sequential Logic Functionality
4. Specify Blocks for Timing Information
5. Modeling Power-Related Aspects (Introduction)
6. Advanced Modeling Techniques

Prerequisites Review

• Assumed Knowledge from Course 1: SystemVerilog syntax, data types (logic, 4-state), modules, ports, parameters, assign, basic procedural blocks (always).
• Assumed Knowledge (Conceptual):
  • Basic Standard Cell functions (AND, OR, MUX, Flip-Flop, Latch).
  • Digital Timing Concepts: Propagation Delay, Setup Time, Hold Time, Clock-to-Q Delay.
  • Static Timing Analysis (STA): Basic idea – tools calculate timing paths without full simulation.
  • Power Concepts: Dynamic Power (switching), Leakage Power.

Learning Objectives

• By the end of this course, you will be able to:
  • Explain the role of SystemVerilog simulation models within an ASIC library context.
  • Model the functionality of combinational and sequential standard cells using SystemVerilog constructs.
  • Use specify blocks to define path delays and timing checks ($setup, $hold, etc.).
  • Understand how Standard Delay Format (SDF) files interact with simulation models.
  • Describe the basic concepts of power intent (UPF) and how models hint at power behavior.
  • Utilize User Defined Primitives (UDPs) and conditional compilation for library modeling.
  • Understand hard-macro and memory macro modeling concepts.

References

• SystemVerilog LRM (Specify Blocks, Primitives, UDPs).
• Liberty Format Specification (for context).
• UPF LRM (Accellera) (Introductory concepts).
• Synopsys Library Compiler Documentation (for context).
• Relevant application notes on library modeling.
• https://github.com/google/skywater-pdk
• Global Foundries 180nm MCU PDK
  • google/gf180mcu-pdk: PDK for GlobalFoundries’ 180nm MCU bulk process technology (GF180MCU).
  • Standard Cells — GlobalFoundries GF180MCU PDK 0.0.0-111-gde3240d documentation