SV.1 SystemVerilog Fundamentals

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About Course

This course, SV.1 – SystemVerilog Fundamentals, serves as the essential technical foundation for senior Electrical Engineering students pursuing careers in Integrated Circuit (IC) Digital Design and Verification.

The primary goal is to establish a solid mastery of SystemVerilog (IEEE 1800) as the industry-standard language, focusing on both its Hardware Description Language (HDL) and Verification Description Language (VDL) capabilities.

The course uniquely emphasizes the core concepts that differentiate hardware description from traditional software programming, such particularly the concepts of 4-State Logic (0, 1, X, Z), Nets vs. Variables, and Concurrent Execution.

The curriculum progresses logically, starting with the context of the ASIC/SOC design flow, moving through fundamental syntax (Module 2), data modeling (Module 3), structural design (Module 4), behavioral logic (Module 5), and concluding with the operational mechanics of Event-Driven Simulation (Module 6), including critical topics like Blocking vs. Non-Blocking Assignments and professional testbench utilities.

Course Content

Module 0. Introduction and Context
The introductory section establishes the need for SystemVerilog by detailing the complexity of modern chip design and positioning the language within the professional flow.

Module 0. Course Introduction and Context

Diancom Foundation

SV.1 SystemVerilog Fundamentals

About Course

Course Content

Module 0. Introduction and Context
The introductory section establishes the need for SystemVerilog by detailing the complexity of modern chip design and positioning the language within the professional flow.

Module 0. Course Introduction and Context

Module 1. Intro to HDL/VDL, IC Design and Verification

Module 1. Intro to HDL/VDL and the IC Design and Verification Flow

Module 2. SV Basic Syntax and Lexical Conventions

Module 2. SV Basic Syntax and Lexical Conventions

Module 3. Data Types

Module 3. Data Types

Module 4. Modules and Basic Structureal Modeling

Module 4. Modules and Basic Structureal Modeling

Module 5. Procedural Blocks and Control Flow

Module 5. Procedural Blocks and Control Flow

Module 6. Event Driven Simulation

Module 6. Event Driven Simulation

Module 7. Simulation Essential Topics

Module 7. Simulation Essential Topics

Module 8. More Simulation System Tasks

Module 8. More Simulation System Tasks

Module 9. Appendix – Event-Driven Simulation Details

Module 9. Appendix – Event-Driven Simulation Details

Module 10. Recap

Module 10. Recap

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Diancom Foundation

About Course

Course Content

Module 0. Introduction and Context The introductory section establishes the need for SystemVerilog by detailing the complexity of modern chip design and positioning the language within the professional flow.

Module 0. Course Introduction and Context

Module 1. Intro to HDL/VDL, IC Design and Verification

Module 1. Intro to HDL/VDL and the IC Design and Verification Flow

Module 2. SV Basic Syntax and Lexical Conventions

Module 2. SV Basic Syntax and Lexical Conventions

Module 3. Data Types

Module 3. Data Types

Module 4. Modules and Basic Structureal Modeling

Module 4. Modules and Basic Structureal Modeling

Module 5. Procedural Blocks and Control Flow

Module 5. Procedural Blocks and Control Flow

Module 6. Event Driven Simulation

Module 6. Event Driven Simulation

Module 7. Simulation Essential Topics

Module 7. Simulation Essential Topics

Module 8. More Simulation System Tasks

Module 8. More Simulation System Tasks

Module 9. Appendix – Event-Driven Simulation Details

Module 9. Appendix – Event-Driven Simulation Details

Module 10. Recap

Module 10. Recap

Quick Links

Contact Us

Module 0. Introduction and Context
The introductory section establishes the need for SystemVerilog by detailing the complexity of modern chip design and positioning the language within the professional flow.